1. Field of the Invention
The present invention relates to a method for processing a digital video image, and more particularly to a method for synchronizing a digital video image when transmitted or received.
2. Description of the Related Art
Conventional digital data systems transmit and receive data in the form of a binary digital signal which includes an unmodulated clock signal. Since there may be a timing skew between an external clock signal and an internal clock signal, such digital data systems must be able to overcome this timing skew problem to accurately recover digital data from a received signal.
To overcome the time skew problem, typically, a clock recovery circuit is used. Particularly, a phase-locked loop (PLL) may be used for clock recovery.
The PLL refers to a phase lock device (circuit) which synchronizes the phase of the received signal. Phase synchronization means controlling an oscillator or a frequency signal generator to maintain a constant phase angle relative to a reference signal. The PLL is widely used in synchronous modulation of a digital modulated wave, coherent carrier tracking, threshold extension, bit synchronization, symbol synchronization and so on. The phase synchronization is accomplished by means of an elastic store (ES) which can independently perform input and output. The elastic store absorbs any phase variation of an input signal which is caused by jitter or delay variation on the transmission path, thereby adjusting the frame phase of the input signal at a particular point of time.
FIG. 1 shows the configuration of a general PLL. As shown in FIG. 1, a general PLL includes a phase/frequency detector 11, a loop filter 12 and a voltage-controlled oscillator 13.
A process for extracting an embedded clock from a received signal using a general PLL will be explained with reference to FIG. 1. When input data is received from an external source, the phase/frequency detector 11 extracts a clock component from the input data and compares the phase of the clock component with that of the voltage-controlled oscillator 13. Any phase difference is detected and is input as an error signal to the loop filter 12. The loop filter 12 filters the error signal input from the phase/frequency detector 11 and compensates for a feedback loop of the PLL to control the voltage-controlled oscillator 13 to extract a clock with a precisely synchronized phase.
The general PLL is configured to recover a clock or data from a data stream with a fixed data bit rate. However, many networks encompass a myriad of data rates so that the general PLL in such networks is problematic. For example, digital video data is transferred at a data rate of 270 Mbps in DVB-ASI (Digital Video Broadcasting-Asynchronous Serial Interface) and at varying data rates of 10 to 80 Mbps in HDTV (High Definition TeleVision). In order to recover data transmitted at such varying data rates, it is critical to recover a clock at each data rate. Therefore, in order to use a conventional PLL in a network encompassing a wide range of data rates, a plurality of PLL circuits that are respectively tuned to different data rates must be provided.
As will be appreciated by one of ordinary skill in the art, a clock recovery circuit using a conventional PLL is complicated, because it has to use different voltage-controlled oscillators (analog devices) depending on data rates. Since the set point is also analog-controlled, the clock recovery circuit is very sensitive and requires more efforts to achieve precise phase synchronization. Also, it is very difficult to implement the clock recovery circuit without using a clock extractor of ordinary data rates.
Therefore, in digital broadcasting or communication environments where clock data must be extracted at different data rates, it is required to change the hardware itself or provide an additional hardware whenever the data rate changes.
Accordingly, there is a need in the art for improved clock recovery mechanisms.